Prof. Joycee Mekie

Professor, Department of Electrical Engineering
Jointly affiliated with Computer Science and Engineering | Indian Institute of Technology Gandhinagar
Email: joycee[at]iitgn.ac.in
Office Phone: +91 (79) 2395 2409
Address: AB13/327-C, Dept. of Electrical Engineering, IIT Gandhinagar, Palaj, Gandhinagar, 382355
✉ Email Contact 🎓 Google Scholar 🆔 ORCID Profile 📚 DBLP

Research Focus Areas

AI Hardware Design Compute-In-Memory Architectures Embedded Memories Approximate Computing Radiation Hardened Circuits/Systems Asynchronous Circuits & Designs Synchronous/Asynchronous Network-on-Chip (NoC)

Awards & Recognitions

Research Grants & Projects

Chips-to-Systems Grant
Sponsor: MEITY
In Memory Computing for Next Generation Workloads Using Emerging Memory Technologies
Sponsor: SERB-SUPRA
Co-PI: Manu Awasthi (Ashoka University)
Fast, Robust, Energy-aware In-Memory Computing Architectures
Sponsor: Semiconductor Research Corporation (SRC), USA
Co-PI: Manu Awasthi (Ashoka University)
Comparative Study of Soft Error Tolerant Synchronous and Asynchronous Processors
Sponsor: SERB-DST
Estimating Error Probabilities due to Multiple Event Transients in Space Applications
Sponsor: MATRICS, SERB-DST
Young Faculty Research Fellowship (YFRF)
Sponsor: MEITY (2018–2023)
Asynchronous and Synchronous Approaches to Network-on-Chip Architecture Design
Sponsor: GIAN (June 2016)
Experimental Studies of Metastability in Different Synchronizers
Sponsor: DST (Fast-Track Scheme, 2012–2016)
Special Manpower Development Project: Chips to System Design (SMDP:C2SD)
Sponsor: MEITY [Co-PI]
SMDP-C2SD Chip Tape-Out Grant for Radiation-Hardened Standard Cell Library
Sponsor: MEITY (2019–2020)

Thesis Supervision

Doctoral Thesis (Ongoing)

Student Topic / Collaboration Joined
Sanjay Markandeya Hardware Security Module for Post-Quantum Cryptography Intern @ NXP India Aug 2025
Bendamuri Mohan Hardware Security Module for Post-Quantum Cryptography Aug 2025
Shruti Mixed-Signal In-Memory Computing for Data Intensive Applications Aug 2025
Sanjay Yadav Energy Efficient Architectures for In-Memory Computing (CDP) Jan 2025
Sri Divya Exploring CMOS-Memristor Logic for In-Memory Computing (CDP) Jan 2025
Himanshu Patel Fault Tolerant RISC-V Accelerators ISRO Collab Aug 2024
Jimit J. Gadhia Energy Efficient Image Enhancement for Space Applications ISRO Collab Aug 2024

Doctoral Thesis (Completed)

Student Topic / Fellowship Graduated
Sneha N. Ved ASOCC: An Evaluation Framework for NoC Architectures Intel Fellow July 2020
Neelam Surana Opportunistic Context-Aware Energy-Efficient Embedded Memory Visvesvaraya Fellow Aug 2020
Chandan Kumar Jha Approximate Designs and Frameworks for Error Resilient Applications Visvesvaraya Fellow Nov 2020
Pramod Kumar Bharti Design and Analysis of Performance-Efficient On-Chip Memories June 2024
Tom Glint Isaac Hardware Accelerators for Emerging ML Workloads Using HW-SW Co-Design June 2024
Kailash Prasad Domain-Specific Hardware Design PM PhD Fellow June 2024

Publications & Presentations

  1. AxLaM: energy-efficient accelerator design for language models for edge computing
    Tom Glint, Bhumika Mittal, Santripta Sharma, Abdul Qadir Ronak, Abhinav Goud, Neerja Kasture, Zaqi Momin, Aravind Krishna, Joycee Mekie.
    Philos Trans A Math Phys Eng Sci 16 January 2025; 383 (2288): 20230395. doi: 10.1098/rsta.2023.0395
  2. Single Exact Single Approximate Adders and Single Exact Dual Approximate Adders
    C. K. Jha, A. Nandi and J. Mekie.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 7, pp. 907-916, July 2023. doi: 10.1109/TVLSI.2023.3268275
  3. HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy
    Sarabjeet Singh, Neelam Surana, Kailash Prasad, Pranjali Jain, Joycee Mekie, and Manu Awasthi.
    ACM Trans. Archit. Code Optim. 20, 2, Article 24 (June 2023), 20 pages. doi: 10.1145/3572839
  4. A 10T, 0.22fJ/Bit/Search Mixed-vt Pseudo Precharge-Free Content Addressable Memory
    Datta, Diptesh, Neelam Surana, Anoop Kumar, and Joycee Mekie.
    IEEE Transactions on Circuits and Systems II: Express Briefs, 2021. doi: 10.1109/tcsii.2021.3103880
  5. Fast and Low-Power Quantized Fixed Posit High-Accuracy DNN Implementation
    S. Walia, B. V. Tej, A. Kabra, J. Devnath and J. Mekie.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 1, pp. 108-111, Jan. 2022. doi: 10.1109/TVLSI.2021.3131609
  6. Zero Aware Configurable Data Encoding by Skipping Transfer for Error Resilient Applications
    C. K. Jha, S. Singh, R. Thakker, M. Awasthi and J. Mekie.
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 8, pp. 3337-3350, Aug. 2021. doi: 10.1109/TCSI.2021.3081623
  7. Fixed-Posit: A Floating-Point Representation for Error-Resilient Applications
    V. Gohil, S. Walia, J. Mekie and M. Awasthi.
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 10, pp. 3341-3345, Oct. 2021. doi: 10.1109/TCSII.2021.3072217
  8. Analysis of Worst-Case Data Dependent Temporal Approximation in Floating Point Units
    C. K. Jha, I. Doshi and J. Mekie.
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 2, pp. 767-771, Feb. 2021. doi: 10.1109/TCSII.2020.3012194
  9. SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol
    S. A. Aketi, S. Gupta, H. Cheng, J. Mekie and P. A. Beerel.
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 5, pp. 1667-1677, May 2020. doi: 10.1109/TCSI.2020.2965073
  10. Energy and Error Analysis Framework for Approximate Computing in Mobile Applications
    C. K. Jha, S. N. Ved, I. Anand and J. Mekie.
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 2, pp. 385-389, Feb. 2020. doi: 10.1109/TCSII.2019.2910137
  11. Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder
    Bharti, Pramod K, N. Surana and J. Mekie.
    IET Computers & Digital Techniques, vol. 13, no.6, pp. 505-513, 2019.
  12. Energy Efficient Single-Ended 6-T SRAM for Multimedia Applications
    N. Surana and J. Mekie.
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 6, pp. 1023-1027, June 2019. doi: 10.1109/TCSII.2018.2869945
  13. PANE: Pluggable Asynchronous Network-on-Chip Simulator
    Ved Sneha N, Sarabjeet Singh and Joycee Mekie.
    ACM Journal Emerging Technologies in Computing Systems, vol. 15, issue 1, article no. 7, January 2019. doi: 10.1145/3241051
  14. Reasoning about Synchronization using Abstract Timing Diagrams
    S. Chakraborty, J. Mekie and D. K. Sharma.
    Formal Methods in System Design (FMSD), Special Issue on GALS Systems, vol. 28, no. 2, pp. 153-169, March 2006.
  1. VeriBench: Benchmarking Large Language Models for Verilog Code Generation and Design Synthesis
    M. Agarwal, Z. Momin, K. Prasad and J. Mekie. IEEE ISCAS, 2025. doi: 10.1109/ISCAS56072.2025.11044004
  2. DTQ-16T: Double Node Upset Tolerant Quadruple SRAM for Space Applications
    P. K. Bharti, G. Prasad, M. P. Kumar and J. Mekie. IEEE ISCAS, 2025. doi: 10.1109/ISCAS56072.2025.11044171
  3. HyCMAx: Power-Efficient Hybrid CMOS-Memristor Based Approximate Dividers for Error-Resilient Applications
    M. Pokharia, H. Trivedi, S. Doshi, R. S. Hegde and J. Mekie. VLSID, 2025. doi: 10.1109/VLSID64188.2025.00092
  4. OwlsEye: Real-Time Low-Light Video Instance Segmentation on Edge and Exploration of Fixed-Posit Quantization
    G. Shah, A. Goud, Z. Momin, J. Mekie. VLSID, 2025. doi: 10.1109/VLSID64188.2025.00090
  5. DeepFrack: A Comprehensive Framework for Layer Fusion, Face Tiling, and Efficient Mapping in DNN Hardware Accelerators
    Tom Glint, Mithil Pechimuthu and Joycee Mekie. DATE, 2024. doi: 10.23919/DATE58400.2024.10546624
  6. COMPRIZE: Assessing the Fusion of Quantization and Compression on DNN Hardware Accelerators
    Vrajesh Patel, Neel Shah, Aravind Krishna, Tom Glint, Abdul Ronak and Joycee Mekie. VLSID, 2024.
  7. Hybrid CMOS-Memristor Logic for Boosting the Power-Efficiency in Error Tolerant Applications Best Poster Paper Award
    Monika Pokharia, Kailash Prasad, Ravi Hegde and Joycee Mekie. VLSID, 2024.
  8. SDR-PUF: Sequence-Dependent Reconfigurable SRAM PUF with an Exponential CRP Space
    Kailash Prasad, Neel Shah, Jinay Dagli and Joycee Mekie. VLSID, 2024.
  9. Robust and High-Performance Digital In-Memory Computing in 5T Gain Cell Embedded DRAM VLSI for Embedded Intelligence
    Prasad, K., Borkar, R., Mekie, J. VDAT 2023, Springer, 2025. doi: 10.1007/978-981-97-3756-7_6
  10. FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC
    Saketh Gajawada, Aryan Gupta, Kailash Prasad and Joycee Mekie. VLSID, 2024.
  11. FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing
    Yathin Attuluri, Ruchit Chudasama, Kailash Prasad and Joycee Mekie. VLSID, 2024.
  12. CANSim: When to Utilize Synchronous and Asynchronous Routers in Large and Complex NoCs
    Tom Glint, Manu Awasthi, Joycee Mekie. ASP-DAC, 2024.
  13. Hardware-Software Co-Design of a Collaborative Accelerator for 3D Stacked Memories with Multi-Channel Data
    Tom Glint, Manu Awasthi, Joycee Mekie. ASP-DAC, 2024.
  14. Hardware-Software Codesign of DNN Accelerators using Approximate Posit Multipliers
    T. Glint et al. ASP-DAC, 2023, pp. 469-474.
  15. Power-Efficient Approximate Multipliers Leveraging Hybrid CMOS-Memristor Paradigm Best Paper Award in WIE
    M. Pokharia, R. Hegde, J. Mekie. APCCAS, 2023.
  16. Analysis of Quantization Across DNN Accelerator Architecture Paradigms
    T. Glint, C. K. Jha, M. Awasthi and J. Mekie. DATE, 2023, pp. 1-2. doi: 10.23919/DATE56975.2023.10136899
  17. Process Variation Resilient Current-Domain Analog In Memory Computing
    K. Prasad, S. Shubham, A. Biswas and J. Mekie. DATE, 2023, pp. 1-2. doi: 10.23919/DATE56975.2023.10137088
  18. PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM Best Paper Nominee
    K. Prasad, A. Biswas, A. Kabra and J. Mekie. DATE, 2023, pp. 1-6. doi: 10.23919/DATE56975.2023.10137338
  19. Fast and Robust Sense Amplifier for Digital In Memory Computing
    K. Prasad, A. Srivastava, N. Baruah and J. Mekie. VLSID, 2023, pp. 258-263. doi: 10.1109/VLSID57277.2023.00060
  20. Hardware-Software Codesign of DNN Accelerators using Approximate Posit Multipliers Best Paper Nominee
    K. Prasad*, T. Glint*, J. Dagli, K. Gandhi, A. Gupta, V. Patel, N. Shah and J. Mekie. IEEE ASPDAC, 2023.
  21. Impact of Operand Ordering in Approximate Multiplication in Neural Network and Image Processing Applications
    Prasad, K., Dagli, J., Shah, N., Pidagannavar, M., Mekie, J. VDAT, 2022. doi: 10.1007/978-3-031-21514-8_46
  22. RTQCC-14T: Radiation Tolerant Quadruple Cross Coupled Robust SRAM Design for Radiation Prone Environments
    Bharti, P.K., Mekie, J. VDAT, 2022. doi: 10.1007/978-3-031-21514-8_40
  23. Compute-In-Memory Using 6T SRAM for a Wide Variety of Workloads
    P. Bharti, S. Jain, K. Pillai, S. Sayyaparaju, G. Kalsi, J. Mekie, S. Subramoney. IEEE ISCAS, 2022.
  24. An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs
    K. Prasad*, A. Parmar*, N. Rao, and J. Mekie. IEEE ISCAS, 2022.
  25. FastMem: A Fast Architecture-aware Memory Layout Design
    A. Parmar, K. Prasad, N. Rao, and J. Mekie. IEEE ISQED, 2022.
  26. RHSCC-16T: Radiation Hardened Sextuple Cross Coupled Robust SRAM Design for Radiation Prone Environments
    Pramod Kumar Bharti, and Joycee Mekie. IEEE ICCD, 2022.
  27. GBRHQ-14T: Gate Boosted Radiation Hardened Quadruple SRAM Design for Space Applications
    Pramod Kumar Bharti, and Joycee Mekie. IEEE ICEE, 2022.
  28. Analysis of Word Line Shaping Techniques for In-Memory Computing in SRAMs
    K. Prasad, A. Biswas and J. Mekie. IEEE ICECS, 2021, pp. 1-6. doi: 10.1109/ICECS53924.2021.9665469
  29. FPCAM: Floating Point Configurable Approximate Multiplier for Error Resilient Applications
    C. K. Jha, S. Walia, G. Kanojia and J. Mekie. IEEE ISCAS, 2021, pp. 1-5.
  30. ANSim: A Fast and Versatile Asynchronous Network-On-Chip Simulator
    T. Glint, J. Sah, M. Awasthi and J. Mekie. IEEE ICCD, 2020, pp. 619-622. doi: 10.1109/ICCD50377.2020.00107
  31. A Low-Voltage Split Memory Architecture for Binary Neural Networks
    J. K. Devnath, N. Surana and J. Mekie. IEEE ISCAS, 2020, pp. 1-5. doi: 10.1109/ISCAS45731.2020.9180862
  32. SEDAAF: FPGA Based Single Exact Dual Approximate Adders for Approximate Processors
    C. K. Jha, K. Prasad, A. S. Tomar and J. Mekie. IEEE ISCAS, 2020, pp. 1-5. doi: 10.1109/ISCAS45731.2020.9181185
  33. FPAD: A Multistage Approximation Methodology for Designing Floating Point Approximate Dividers
    C. K. Jha, K. Prasad, V. K. Srivastava and J. Mekie. IEEE ISCAS, 2020, pp. 1-5.
  34. Tunable Inexact Subtracters for Division in Image Processing Applications
    A. Nandi, C. K. Jha and J. Mekie. IEEE MWSCAS, 2020, pp. 1100-1103. doi: 10.1109/MWSCAS48704.2020.9184460
  35. Robust and High-Performance 12-T Interlocked SRAM for In-Memory Computing
    N. Surana, M. Lavania, A. Barma and J. Mekie. DATE, 2020, pp. 1323-1326. doi: 10.23919/DATE48585.2020.9116361
  36. A Mathematical Approach Towards Quantization of Floating Point Weights in Low Power Neural Networks
    J. K. Devnath, N. Surana and J. Mekie. VLSID, 2020, pp. 177-182. doi: 10.1109/VLSID49098.2020.00048
  37. Quality Tunable Approximate Adder for Low Energy Image Processing Applications
    C. K. Jha, A. Nandi and J. Mekie. IEEE ICECS, 2019, pp. 642-645. doi: 10.1109/ICECS46596.2019.8965205
  38. Should We Code Differently When Using Approximate Circuits?
    A. Nandi, C. K. Jha and J. Mekie. IEEE APCCAS, 2019, pp. 37-40. doi: 10.1109/APCCAS47518.2019.8953113
  39. Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based Designs
    C. K. Jha and J. Mekie. Euromicro DSD, 2019, pp. 174-181. doi: 10.1109/DSD.2019.00034
  40. SEDA - Single Exact Dual Approximate Adders for Approximate Processors
    C. K. Jha and J. Mekie. ACM/IEEE DAC, 2019, pp. 1-2.
  41. Read-Decoupled Radiation Hardened RD-DICE SRAM Cell for Low-Power Space Applications
    M. Lavania, N. Surana, I. Anand and J. Mekie. IEEE EDSSC, 2019, pp. 1-3. doi: 10.1109/EDSSC.2019.8753939
  42. Energy and Area Efficient 11-T Ternary Content Addressable Memory for High-Speed Search
    D. Datta, P. Dewangan, N. Surana and J. Mekie. IEEE EDSSC, 2019, pp. 1-3. doi: 10.1109/EDSSC.2019.8754423
  43. Soft Error Resilient and Energy Efficient Dual Modular TSPC Flip-Flop Best Paper Nominee
    S. Gupta and J. Mekie. VLSID, 2019, pp. 341-346. doi: 10.1109/VLSID.2019.00077
  44. Power and Area Efficient Approximate Heterogeneous 8T SRAM for Multimedia Applications
    P. K. Bharti, N. Surana and J. Mekie. VLSID, 2019, pp. 139-144. doi: 10.1109/VLSID.2019.00043
  45. Impact of Variations on Synchronizer Performance: An Experimental Study
    J. Mekie, P. Mukim and K. Kale. VLSID, 2018, pp. 459-460. doi: 10.1109/VLSID.2018.112
  46. Single-Error Hardened and Multiple-Error Tolerant Guarded Dual Modular Redundancy Technique
    S. A. Aketi, J. Mekie and H. Shah. VLSID, 2018, pp. 250-255. doi: 10.1109/VLSID.2018.71
  47. Upset hardened latch as data synchronizer
    N. Kumari and J. Mekie. IEEE EDSSC, 2017, pp. 1-2. doi: 10.1109/EDSSC.2017.8126562
  48. Impact of high-Îș spacer on circuit level performance of junctionless FinFET
    N. Surana, J. Mekie and N. R. Mohapatra. IEEE EDSSC, 2017, pp. 1-2. doi: 10.1109/EDSSC.2017.8126574
  49. Route-on-Fly: A single cycle router
    S. N. Ved, A. Bhange, A. Arya and J. Mekie. IEEE SPIN, 2017, pp. 109-114. doi: 10.1109/SPIN.2017.8049926
  50. A comparative study of input port and crossbar configurations in NoC router microarchitectures
    S. N. Ved, A. Arya, A. Bhange and J. Mekie. IEEE SPIN, 2017, pp. 121-125. doi: 10.1109/SPIN.2017.8049928
  51. Short and deep drain MOSFET for space applications: Device and circuit level analysis
    N. Surana, R. Kaur and J. Mekie. IEEE RADECS, 2016, pp. 1-4. doi: 10.1109/RADECS.2016.8093169
  52. Guarded dual rail logic for soft error tolerant standard cell library
    R. Kaur, N. Surana and J. Mekie. IEEE RADECS, 2016, pp. 1-4. doi: 10.1109/RADECS.2016.8093144
  53. A holistic comparison of static VC allocation versus dynamic VC allocation based NoC routers
    S. N. Ved, A. Gour, A. Arya and J. Mekie. IEEE ICEE, 2016, pp. 1-4. doi: 10.1109/ICEmElec.2016.8074419
  54. Fault tolerant tactile sensor arrays for prosthesis
    S. Teja, J. Mekie, J. -J. Cabibihan, N. V. Thakor and S. L. Kukreja. IEEE BioRob, 2016, pp. 31-34. doi: 10.1109/BIOROB.2016.7523594
  55. Impact of Optimal Design Point on Performance Metrics of DNN accelerators in FPGA
    T. Glint, A. Gupta, D. Giftson, G. Shah, V. Patel, R. Chudasama, S. More and J. Mekie. IEEE ISPASS, 23 Jun 2023.
  56. REDRAW: Fast and Efficient Hardware Accelerator with Reduced Reads And Writes for 3D UNet
    T. Glint, M. Awasthi and J. Mekie. DATE, 2 Jun 2023. doi: 10.23919/DATE56975.2023.1013719
  57. Analysis of Conventional, Near-Memory, and In-Memory DNN Accelerators
    T. Glint, C. K. Jha, M. Awasthi and J. Mekie. IEEE ISPASS, 23 Jun 2023. doi: 10.1109/ISPASS57527.2023.00049
  58. PVC-RAM: Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs
    S. Shubham, S. Pandit, K. Prasad and J. Mekie. ACM/IEEE DAC, 15 Sep 2023. doi: 10.1109/DAC56929.2023.10247893
  59. Mixed-8T: Energy-Efficient Configurable Mixed-VT SRAM Design Techniques for Neural Networks
    N. Surana, P. K. Bharti, B. V. Tej and J. Mekie. VLSID, 14 Sep 2022. doi: 10.1109/VLSID2022.2022.00043
  60. Effect of Dynamic Frequency Scaling on Interface Design for Rationally-Related Multi-clocked Systems
    J. Mekie. IEEE ASYNC, Potsdam, Germany, 2014, pp. 37-44. doi: 10.1109/ASYNC.2014.13
  61. Interface design for rationally clocked GALS systems
    J. Mekie, S. Chakraborty, G. Venkataramani, P. S. Thiagarajan and D. K. Sharma. IEEE ASYNC, Grenoble, France, 2006, pp. 12 pp.-171. doi: 10.1109/ASYNC.2006.19
  62. Evaluation of pausible clocking for interfacing high speed IP cores in GALS framework
    J. Mekie, S. Chakraborty and D. K. Sharma. IEEE International Conference on VLSI Design, Mumbai, India, 2004, pp. 559-564. doi: 10.1109/ICVD.2004.1260978

Tutorials at International Conferences

  1. Tutorial T7B: Network on Chips - The Journey Overview
    J. Mekie and S. N. Ved. 27th International Conference on VLSI Design and 13th International Conference on Embedded Systems, Mumbai, India, 2014.

Invited Talks & Keynotes

  1. Approximate circuits and systems for error-resilient applications — C.K. Jha and J. Mekie, Poster at Intel Research Colloquium, Bangalore, Oct 22, 2019.
  2. Approximate Computing and Storage for low power VLSI Applications — J. Mekie, GujCOST sponsored workshop, Indus University, Ahmedabad, 28 Aug, 2019.
  3. Energy-Efficient Hardware for AI/ML — J. Mekie, Keynote at ACM-W India Celebrations of Women in Computing (AICWiC 2019), IITGN, July 13, 2019.
  4. Approximate Memories for Multimedia Applications — J. Mekie, GTU-ISTE FDP on Research Opportunities in VLSI & Signal Processing, VGEC, 13 Feb 2019.
  5. Internet of things (IoT) using Intel Galileo — J. Mekie, National workshop at BVM Engineering College, Vidyanagar, 22 Aug 2016.
  6. Intel Galileo platform for IOT — J. Mekie, STTP on Embedded Systems and IoT, BVM, Vidyanagar, 8 Jan 2016.
  7. Network on chips at IITGN — S. N. Ved and J. Mekie, Poster at Intel Academic forum (IAF), Bangalore, Oct 2015.
  8. Intel higher education program at IITGN — J. Mekie, Poster at Intel Academic forum (IAF), Bangalore, Oct 2015.
  9. Building new generation chips using asynchronous logic — J. Mekie, Poster at Intel Asia Innovation Summit, Taiwan, Nov 2014.
  10. Research overview in multi-core architectures — J. Mekie, Research scholars meet of TEQIP colleges, IPR, Ahmedabad, Nov 2015.
  11. Women Engineer and Career — J. Mekie, Panel member, WIE special track, IEEE VDAT, Ahmedabad, June 2015.
  12. Network on chip architectures — J. Mekie, STTP on Recent developments in VLSI and Image processing, VGEC, Gujarat, May 2015.
  13. An overview of Asynchronous circuit design — J. Mekie, STTP on Recent developments in VLSI and Image processing, VGEC, Gujarat, May 2015.
  14. Research in VLSI design — J. Mekie, Invited lecture, Parul Institute, Vadodara, May 2015.
  15. Overview of Network-on-Chip architectures — J. Mekie, STTP at Marwadi Institute, Rajkot, March 19, 2015.
  16. Higher education in premier institutions and future prospects — J. Mekie, Techfest FELICIFIC 2015, DDU, Nadiad, March 11, 2015.
  17. Research in VLSI design — J. Mekie, GEC Gandhinagar, Jan 2015.
  18. Building new generation chips using Asynchronous logic — J. Mekie, Intel Asia Innovation Summit, Taipei, TW, Nov. 18-19, 2014.
  19. Interfacing solutions for Globally asynchronous locally synchronous designs — J. Mekie, Innovations for High Performance (iHP), Germany, May 2014.
  20. Network-on-Chip architectures — J. Mekie, STTP on VLSI Signal processing, Nagpur, March 2014.
  21. Globally asynchronous, Locally-synchronous Designs — J. Mekie, STTP on VLSI Signal processing, Nagpur, March 2014.
  22. Innovations and Emerging Trends in Embedded Systems and VLSI Design — J. Mekie, Keynote at NCIET, Jan 2014.
  23. Asynchronous circuit design — J. Mekie, Parul Institute, Vadodara, Jan 2014.
  24. Network-on-Chip architectures — J. Mekie, Parul Institute, Vadodara, Jan 2014.
  25. Globally asynchronous, Locally-synchronous Designs — J. Mekie, IEEE INDICON, Mumbai, Dec 2013.
  26. Emerging Trends in Embedded Systems and VLSI Design — J. Mekie, NCEVT, Anand, May 2013.
  27. Reasoning about timing in multi-clocked systems: A tool demo — J. Mekie, G. Samuel, S. Garg and S. Chakraborty, Workshop on Formal Methods, IIT Bombay, June 2005.

Continuing Education Programs (CEP) Conducted

  1. Hands-on Workshop on Embedded systems and Internet-of-Things with Intel Galileo — May 4-5, 2015.
  2. Workshop on Embedded systems and Internet-of-Things — Sponsored by Intel India Higher Education Program, April 30-May 2, 2015.
  3. Embedded systems for Low cost automation — Lectures/labs for CEP on Low-Cost Hi-Tech Automation (LCHA), Oct 2015, May 2015, Sept 2014, May 2014.
  4. Low-cost automation: Electronics perspective — CEP Course on LCHA, Nov 2013.
  5. Role of Electronics in Low-cost automation — CEP Course conducted at Ashok Leyland, January 2010.

Professional Leadership & Service

Journal & Conference Reviewer

  • Journal Reviewer: Nature Electronics (2025), IEEE Design & Test, IEEE Sensors Journal, IEEE TCAS-I, IEEE TCAS-II, Microelectronics Reliability
  • Conference Reviewer: IEEE ISCAS, DAC 2024, VLSID 2024
  • Steering & Program Committee: ASYNC (2015, 2016), VLSID (2024–2026), ISLPED (2025)

Track & Committee Leadership

  • Track Co-Chair: VLSID (2026, 2025, 2024), ISLPED (2025)
  • WIE Chair / Co-Chair: iSES 2024, VDAT 2022, VLSID 2021
  • Education Chair: IEEE VDAT 2015, Ahmedabad
  • Session Chair: iSES 2023, VLSID 2018