People

Current Ph.D. Students

• Sneha N Ved
• Neelam Surana
• Chandan Kumar Jha
• Pramod Kumar
• Tom Glint Isaac
• Kailash Prasad

Current M.Tech

• Ankita Nandi
• Jitesh Sah
• Gyanendra Tiwari - Placed at NXP Semiconductors
• Diptesh Datta - Placed at Redpine Signals
• Surendra Maurya - Placed at SiliConch Systems

Current B.Tech

• Sumit Walia
• Pranjali Jain
• Shreyas Singh
• Deepika Soni
• Shweta Pardeshi

Research Staff

• Joydeep Devnath
• Vibhor Srivastava

Alumni M.Tech

2019

• Arun Singh Tomar - Thesis Title Configurable Approximate Circuits for Low Power FPGA based Applications - Working as Design Verification Engineer at Marvell Semiconductor
• Mili Lavania - Thesis Title Building Energy Efficient Radiation Hardened Memories and Memory Subsystem - Working as Design Verification Engineer at Marvell Semiconductor
• Abhishek Barma -Thesis Title High Performance Radiation Hardened Random Access and Content Addressable Memory Designs - Working as Silicon Design Engineer at Advanced Micro Devices
• Joydeep Devnath - Thesis Title An approach towards building Energy Efficient Architectures for Neural Networks - Working as Junior Research Fellow at IIT Gandhinagar

2018

• Shubhanshu Gupta - Thesis Title Single and Double Node Upset Hardened Flip-Flops for Space Applications - Working as Design Verification Engineer at NXP Semiconductor
• Ishant Anand - Thesis Title Design of Radiation Hardened Memories and Memory Compiler - Working as Senior Engineer at MediaTek
• Smriti Gupta - Thesis Title ** - **Building of Radiation Hardened Processor Designs - Working as Engineer at MediaTex
• Vishwanath Hiremath - Thesis Title Approximate Neural Networks on FPGA - Working as Senior Engineer at MediaTek

2017

• Hemal Shah - Thesis Title Soft Error Tolerant Designs using Guarded Dual Rail Logic - Working as Design Verification Engineer at Marvell Semiconductor
• Neha Kumar - Thesis Title Interfaces for Ratiochronous Network on Chips - Working as Senior Tapeout Engineer at GlobalFoundries

2016

• Raminder Kaur - Thesis Title Guarded Dual Rail Logic for Soft Error Tolerant Standard Cell Library - Working as Digital Verification Engineer at Texas Instruments
• Omkar Pujari - Thesis Title Study of Variability and Technology Scaling on  Synchronizers and Design of Metastable-hard Synchronizers - Working as Digital Design Engineer at Analog Devices

2015

• Fathima Sinin - Thesis Title Design and implementation of efficient neuromorphic architectures - Working as Air Traffic Controller at Airport Authority of India
• Chandrashekhar Tunga - Thesis Title ** - Working as Senior Lead Engineer at Qualcomm

2014

• Bala Saranya Y - Thesis Title Evaluating the scaling effects on synchronizers and global interconnects in multi-core SoCs - Working as SSC at Infosys

Alumni B.Tech

• Sai Aparna Aketi
• Anmol Gaur
• L Madhulika